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CS4373A Low-power, High-performance Test DAC
Features
Digital Input from CS5376A Digital Filter Selectable Differential Analog Outputs
* Precision output (OUT) for electronics tests * Buffered output (BUF) for sensor tests
Description
The CS4373A is a high-performance, differential output digital-to-analog converter (DAC) with programmable attenuation and multiple operational modes. AC test modes measure system dynamic performance through THD and CMRR tests while DC test modes are for gain calibration and pulse tests. The CS4373A is driven by a digital bit stream from the CS5376A digital filter test bit stream (TBS) generator. It has two sets of differential analog outputs, OUT and BUF, to simplify system design as dedicated outputs for testing the electronics channel and for in-circuit sensor tests. Analog output attenuation is selected by simple pin settings and matches the gain of the CS3301A / CS3302A differential amplifiers for full-scale testing at all gain ranges. calibration capability for high-resolution, low-frequency multi-channel measurement systems designed from CS3301A / CS3302A differential amplifiers, CS5371A / CS5372A modulators and the CS5376A digital filter.
Multiple AC and DC Operational Modes
* Signal bandwidth: DC to 100 Hz * Max AC amplitude: 5 VPP differential * Max DC amplitude: + 2.5 Vdc differential
Selectable Attenuation for CS3301A / CS3302A
* 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64
Outstanding Performance
* AC (OUT): -116 dB THD typical, -112 dB max * AC (BUF): -108 dB THD typical, -90 dB max * DC absolute accuracy: 0.4% typical, 1% max The CS4373A test DAC provides self-test and precision
Low Power Consumption
* AC modes / DC modes: 40 mW / 20 mW * Sleep mode / Power Down: 1 mW / 10 W
Extremely Small Footprint
* 28-pin SSOP package, 8 mm x 10 mm
Bipolar Power Supply Configuration
* VA+ = +2.5 V;VA- = -2.5 V; VD = +3.3 V
ORDERING INFORMATION See page 34.
VA+
MODE(0, 1, 2)
ATT(0, 1, 2)
VD
TDATA Attenuator
OUT+ OUT24-Bit DAC BUF+ BUF-
VREF+ VREFClock Generator MCLK MSYNC
VA-
CAP+ CAP-
GND
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2006 (All Rights Reserved)
DEC `06 DS699F2
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TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 2. GENERAL DESCRIPTION ..................................................................................................... 16 2.1 Digital Inputs .................................................................................................................... 16 2.2 Analog Outputs ................................................................................................................ 16 2.3 Multiple Operational Modes ............................................................................................. 16 2.4 Low Power ....................................................................................................................... 16 3. SYSTEM DIAGRAMS .......................................................................................................... 17 4. POWER MODES ..................................................................................................................... 18 4.1 Power Down ..................................................................................................................... 18 4.2 Sleep Modes .................................................................................................................... 18 4.3 AC Test Modes ................................................................................................................ 18 4.4 DC Test Modes ................................................................................................................ 18 5. OPERATIONAL MODES ........................................................................................................ 19 5.1 Sleep Modes .................................................................................................................... 19 5.2 AC Test Modes ................................................................................................................ 19 5.2.1 AC Differential ..................................................................................................... 19 5.2.2 AC Common Mode .............................................................................................. 20 5.2.3 AC Stability .......................................................................................................... 20 5.3 DC Test Modes ................................................................................................................ 20 5.3.1 DC Common Mode ............................................................................................. 20 5.3.2 DC Differential ..................................................................................................... 20 6. DIGITAL INPUTS .................................................................................................................... 22 6.1 TDATA Connection .......................................................................................................... 22 6.2 MCLK Connection ............................................................................................................ 22 6.3 MSYNC Connection ......................................................................................................... 22 6.4 GPIO Connections ........................................................................................................... 23 7. ANALOG OUTPUTS ............................................................................................................... 24 7.1 Differential Signals ........................................................................................................... 24 7.2 Analog Output Attenuation ............................................................................................... 24 7.3 OUT Precision Output .................................................................................................... 25 7.4 BUF Buffered Output ..................................................................................................... 25 7.5 CAP Analog Output ........................................................................................................ 25 8. VOLTAGE REFERENCE ........................................................................................................ 26 8.1 VREF Power Supply ........................................................................................................ 26 8.2 VREF RC Filter ................................................................................................................ 26 8.3 VREF PCB Routing .......................................................................................................... 26 8.4 VREF Input Impedance .................................................................................................... 27 8.5 VREF Accuracy ................................................................................................................ 27 8.6 VREF Independence ....................................................................................................... 27 9. POWER SUPPLIES ................................................................................................................ 28 9.1 Power Supply Bypassing ................................................................................................. 28 9.2 PCB Layers and Routing ................................................................................................. 28 9.3 Power Supply Rejection ................................................................................................... 28 9.4 SCR Latch-up .................................................................................................................. 29 9.5 DC-DC Converters .......................................................................................................... 29 10. TERMINOLOGY .................................................................................................................... 30 11. PIN DESCRIPTION ............................................................................................................... 31 12. PACKAGE DIMENSIONS ..................................................................................................... 33 13. ORDERING INFORMATION ................................................................................................ 34 14. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION .......................... 34 15. REVISION HISTORY ........................................................................................................... 34
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LIST OF FIGURES
Figure 1. Digital Input Rise and Fall Times ................................................................................... 12 Figure 2. System Timing Diagram................................................................................................. 14 Figure 3. MCLK / MSYNC Timing Detail ....................................................................................... 14 Figure 4. CS4373A Block Diagram ............................................................................................... 16 Figure 6. Connection Diagram ...................................................................................................... 17 Figure 5. System Diagram ............................................................................................................ 17 Figure 7. Power Mode Diagram .................................................................................................... 18 Figure 8. AC Differential Modes .................................................................................................... 19 Figure 9. AC Common Mode ........................................................................................................ 20 Figure 10. DC Test Modes ............................................................................................................ 21 Figure 11. Digital Inputs ................................................................................................................ 22 Figure 12. Analog Outputs ............................................................................................................ 24 Figure 13. Voltage Reference Circuit ............................................................................................ 26 Figure 14. Power Supply Diagram ................................................................................................ 28
LIST OF TABLES
Table 1. Selections for Operational Mode and Attenuation............................................................. 4 Table 2. Operational Modes.......................................................................................................... 19 Table 3. Output Attenuation Settings ............................................................................................ 24
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1.
* * * *
CHARACTERISTICS AND SPECIFICATIONS
Min / Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are measured at nominal supply voltages and TA = 25C. GND = 0 V. Single-ended voltages with respect to GND, differential voltages with respect to opposite half. Device is connected as shown in Figure 6 on page 17, unless otherwise noted.
SPECIFIED OPERATING CONDITIONS
Parameter Bipolar Power Supplies Positive Analog Negative Analog Positive Digital Voltage Reference Input {VREF+} - {VREF-} VREFThermal Ambient Operating Temperature Industrial (-IS, -ISZ) TA -40 25 85 C (Note 2, 3) (Note 4) VREF VREF2.500 VA V V Symbol Min 2.45 -2.45 3.20 Nom 2.50 -2.50 3.30 Max 2.55 -2.55 3.40 Unit V V V
2% (Note 1) 2% 3%
VA+ VAVD
Notes: 1. VA- must always be the most-negative input voltage to avoid potential SCR latch-up conditions. 2. By design, a 2.500 V voltage reference input results in the best signal-to-noise performance. 3. Full-scale accuracy is directly proportional to the voltage reference absolute accuracy. 4. VREF inputs must satisfy: VA- < VREF- < VREF+ < VA+.
Modes of Operation Selection 0 1 2 3 4 5 6 7 MODE[2:0] 000 001 010 0 11 100 101 11 0 111 Mode Description Sleep mode. AC OUT and BUF outputs. AC OUT only, BUF high-z. AC BUF only, OUT high-z. DC common mode output. DC differential output. AC common mode output. Sleep mode. Selection 0 1 2 3 4 5 6 7
Attenuation ATT[2:0] 000 001 010 0 11 100 101 11 0 111 Attenuation 1/1 1/2 1/4 1/8 1/16 1/32 1/64 reserved dB 0 dB -6.02 dB -12.04 dB -18.06 dB -24.08 dB -30.10 dB -36.12 dB reserved
Table 1. Selections for Operational Mode and Attenuation
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TEMPERATURE CONDITIONS
Parameter Ambient Operating Temperature Storage Temperature Range Allowable Junction Temperature Junction to Ambient Thermal Impedance (4-layer PCB) Symbol TA TSTG TJCT JA Min -40 -65 -
Typ 65
Max +85 150 125
-
Unit C C C C / W
ABSOLUTE MAXIMUM RATINGS
Parameter DC Power Supplies Positive Analog Negative Analog Digital (VA+) - (VA-) (VD) - (VA-) (Note 5) (Note 5) (Note 5) Symbol VA+ VAVD VADIFF VDDIFF IIN IIN IOUT PDN VINA VIND Min -0.5 -6.8 -0.5 (VA-) - 0.5 -0.5 Max 6.8 0.5 6.8 6.8 7.6 Parameter V V V V V mA mA mA mW V V
Analog Supply Differential Digital Supply Differential Input Current, Power Supplies Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltages Digital Input Voltages
50 10 25
500 (VA+) + 0.5 (VD) + 0.5
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 5. Transient currents up to 100 mA will not cause SCR latch-up.
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ANALOG CHARACTERISTICS
Parameter VREF Input {VREF+} - {VREF-} VREFVREF Input Current, AC modes VREF Input Current, DC modes VREF Input Noise Analog OUT Output Analog External Load at OUT (Note 7, 8) Differential Output Impedance Load Resistance Load Capacitance 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 (Note 8) (Note 8) Load Resistance Load Capacitance 1/1 - 1/64 1/1 - 1/32 (Note 9) (BUF-) 1/64 (Note 9) (BUF+) 1/64 (Note 8) (Note 8) RLOUT CLOUT ZDIFOUT 50 1 1.4 10.1 7.9 5.1 3.3 2.3 1.7 0.7 7.4 9.0 9.4 9.5 9.5 9.4 3 -120 6 3 3 50 4.5 -120 50 2 M pF k k k k k k k k k k k k k k M dB k nF (Note 6) (Note 2, 3) (Note 4) VREF VREFVREFIAC VREFIDC VREFIN 2.500 VA 80 40 1 V V A A Vrms Symbol Min Typ Max Unit
Single-ended Output Impedance
ZSEOUT
High-Z Impedance Crosstalk to BUF High-Z Output Analog BUF Output Analog External Load at BUF (Note 8) Differential Output Impedance Single-ended Output Impedance
HZOUT XTOUT RLBUF CLBUF ZDIFBUF ZSEBUF
High-Z Impedance Crosstalk to OUT High-Z Output
HZBUF XTBUF
M dB
Notes: 6. Maximum integrated noise over the measurement bandwidth for the voltage reference device attached to the VREF inputs. 7. Load on the precision OUT outputs is normally from the CS3301A / CS3302A amplifiers, which have 1 G/1 T typical input impedance and 18 pF typical input capacitance. 8. Guaranteed by design and/or characterization. 9. Single-ended output impedance at 1/64 is different for BUF+ and BUF- due to the output attenuator architecture.
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AC DIFFERENTIAL MODES 1, 2, 3
Parameter AC Differential Characteristics Full-scale Differential AC Output 1/1 1/2 1/4 1/8 1/16 1/32 1/64 (Note 8) (Note 8, 10) 1/1
1/2 1/4 1/8 1/16 1/32 1/64
Symbol VACFS
Min - 0.5
- 0.2 -
Typ 5 2.5 1.25 625 312.5 156.25 78.125 - 0.2
0.1 0.1 0.1 - 0.1 0.2 - 0.2 0.3 - 0.5 0.5
Max 100 -20 0.2
0.2 -
Unit Vpp Vpp Vpp mVpp mVpp mVpp mVpp Hz dBfs %FS
% % % % % %
Full-scale Bandwidth Impulse Amplitude AC Differential Accuracy Full-scale Accuracy (Note 3, 11) Relative Accuracy (Note 12)
VACBW VACIMP VACABS VACREL
Full-scale Drift DC Common Mode Characteristics Common Mode Common Mode Drift
(Note 14) (Note 13)
VACTC VACCM
-
25
(VA-)+2.35
-
V/C V V/C
(Note 13, 14) VACCMTC
300
Notes: 10. Maximum amplitude for operation above 100 Hz. A reduced amplitude for higher frequencies is required to guarantee stability of the low-power delta-sigma architecture. 11. Full-scale accuracy compares the defined full-scale 1/1 amplitude to the measured 1/1 amplitude. Specification is for unloaded outputs. Applying a differential load lowers the output amplitude ratiometric to the differential output impedance. 12. Relative accuracy compares the measured 1/2,1/4,1/8,1/16,1/32,1/64 amplitude to the measured 1/1 amplitude. 13. Common mode voltage is defined as [(SIG+) + (SIG-)] / 2. 14. Specification is for the parameter over the specified temperature range and is for the device only. It does not include the effects of external components.
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AC DIFFERENTIAL MODES 1, 2, 3 (CONT.)
Parameter Signal to Noise Signal to Noise (OUT Unloaded) (Note 15) 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x SNROUT 114 114 114 113 111 108 103 110 106 101 95 89 83 77 - 116 - 115 - 114 - 112 - 111 - 110 - 106 - 108 - 105 - 100 - 94 - 88 - 82 - 76 - 102 - 101 - 97 - 92 - 87 - 82 - 76 - 112 - 90 - 80 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Symbol Min Typ Max Unit
Signal to Noise (BUF Unloaded, 1 k Load) (Note 15, 16)
SNRBUF
Total Harmonic Distortion Total Harmonic Distortion (OUT Unloaded) (Note 17, 18) THDOUT
Total Harmonic Distortion (BUF Unloaded) (Note 16, 17, 18)
THDBUF
Total Harmonic Distortion (BUF 1 k Load) (Note 16, 17, 18)
THDBUFL
Notes: 15. Specification measured using CS3301A amplifier at corresponding gain with the CS5371A / CS5372A modulator measuring a 430 Hz bandwidth. Amplified noise dominates for x16, x32, x64 amplifier gains. 16. Buffered outputs (BUF) include 1/f noise not present on the precision outputs (OUT). 17. Tested with a 31.25 Hz sine wave at -1 dB amplitude. 18. Specification measured using CS3301A amplifier at corresponding gain using the CS5371A / CS5372A modulator measuring a 430 Hz bandwidth. Amplified noise in the harmonic bins dominates THD measurements for x16, x32, x64 amplifier gains.
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DC COMMON MODE 4
Parameter DC Common Mode Characteristics Common Mode Output Common Mode Drift DC Common Mode Accuracy Common Mode Match Noise Noise (OUT Unloaded) (Note 15) 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x NOUT 6 7 7 7 7 9 14 7 10 17 33 64 130 257 Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms 1/1 VDCCMM -5 1 5 mV VDCCM (Note 14) VDCCMTC (VA-)+2.35
Symbol
Min
Typ
Max -
Unit V V/C
300
Noise (BUF Unloaded, 1 k Load) (Note 15, 16)
NBUF
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DC DIFFERENTIAL MODE 5
Parameter DC Differential Mode Characteristics Full-scale Differential DC Output (Note 19) 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1
1/2 1/4 1/8 1/16 1/32 1/64
Symbol VDCFS
Min - 1.0
- 0.2 -
Typ 2.5 1.25 625 312.5 156.25 78.125 39.0625 - 0.4
0.1 0.1 -0.1 0.4 -0.2 0.9 -0.5 1.7 -1.0 3.6
Max 0.2
0.2 -
Unit V V mV mV mV mV mV %FS
% % % % % %
DC Differential Accuracy Full-scale Accuracy (Note 3, 11) Relative Accuracy (Note 12) VDCABS VDCREL
Full-scale Drift DC Common Mode Characteristics Common Mode Common Mode Drift Noise Noise (OUT Unloaded) (Note 15, 19)
(Note 14) (Note 13)
VDCTC VDCCM
-
25
(VA-)+2.35
-
V/C V V/C Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms Vrms
(Note 13, 14) VDCCMTC 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/1 1/2 1/4 1/8 1/16 1/32 1/64 -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x -> 1x -> 2x -> 4x -> 8x -> 16x -> 32x -> 64x NOUT
300 9 9 9 9 10 11 15 10 12 18 32 67 122 265
Noise (BUF Unloaded, 1 k Load) (Note 15, 16, 19)
NBUF
Notes: 19. DC differential output is chopper stabilized and includes low-level 32 kHz out-of-band noise which is rejected by the digital filter during acquisition.
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AC COMMON MODE 6
Parameter AC Common Mode Characteristics Full-scale Common Mode AC Output (Note 20) 1/1 1/2 1/4 1/8 1/16 1/32 (Note 8) (Note 8, 10) VCMFS 2.5 1.25 625 312.5 156.25 78.125 -115 -95 - 0.3 - 0.1 - 0.5 - 1.0 -2.0 -5.0 25
(VA-)+2.35
Symbol
Min
Typ
Max 100 -20 -105 -85 -
Unit Vpp Vpp mVpp mVpp mVpp mVpp Hz dBfs dB dB %FS % % % % % V/C V V/C
Full-scale Bandwidth Impulse Amplitude AC Common Mode Accuracy Common Mode Match (OUT Unloaded) (Note 17, 20)
VCMBW VCMIMP VCMCMM VCMCMM
Common Mode Match (BUF Unloaded, 1 k Load) (Note 16, 17, 20) Full-scale Accuracy (Note 3, 11) Relative Accuracy (Note 12, 20) 1/1 1/2 1/4 1/8 1/16 1/32 (Note 14) (Note 21)
VACABS VACREL
Full-scale Drift DC Common Mode Characteristics Common Mode Mean Common Mode Mean Drift
VCMTC VCMCM
(Note 14, 21) VCMCMTC
300
Notes: 20. No AC common mode signal is output at 1/64 attenuation due to the attenuator architecture. 21. Common mode mean is defined as [(SIGmax) + (SIGmin)] / 2.
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DIGITAL CHARACTERISTICS
Parameter Digital Inputs High-level Input Drive Voltage Low-level Input Drive Voltage Input Leakage Current Digital Input Capacitance Rise Times Except MCLK Fall Times Except MCLK TDATA Input TDATA Input Bit Rate TDATA Input One's Density Range TBSGAIN Full-scale Code TBSGAIN -20 dB Code (Note 23) (Note 8) (Note 24) (Note 24) ftdata INROD TBSFS TBS-20dB 25 256 0x04B8F2 0x0078E5
Symbol (Note 22) (Note 22) (Note 8) (Note 8) (Note 8) VIH VIL IIN CIN tRISE tFALL
Min 0.6*VD 0.0 -
Typ +1 9 -
Max VD 0.8 +10 100 100 75 -
Unit V V A pF ns ns kbits/s %
Notes: 22. Device is intended to be driven with CMOS logic levels. 23. TDATA is generated by the test bit stream generator in the CS5376A digital filter. 24. TBSGAIN register value in the CS5376A digital filter.
t rise
t fall 0.9 * VD 0.1 * VD
Figure 1. Digital Input Rise and Fall Times
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DIGITAL CHARACTERISTICS (CONT.)
Parameter Master Clock MCLK Frequency MCLK Period MCLK Duty Cycle MCLK Rise Time MCLK Fall Time MCLK Jitter (In-band or aliased in-band) MCLK Jitter (Out-of-band) Master Sync MSYNC Setup Time to MCLK rising MSYNC Period MSYNC Hold Time after MCLK falling MSYNC Instant to TDATA Start (Note 8, 26) (Note 8, 26) (Note 8, 26) (Note 8, 27) tmss tmsync tmsh ttdata 20 40 20 122 976 122 1220 ns ns ns ns (Note 25) (Note 25) (Note 8) (Note 8) (Note 8) (Note 8) fCLK tmclk MCLKDC tRISE tFALL MCLKIBJ 40 2.048 488 60 50 50 300 1 MHz ns % ns ns ps ns Symbol Min Typ Max Unit
(Note 8) MCLKOBJ
Notes: 25. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the device automatically enters a power-down state. 26. MSYNC is generated by the CS5376A digital filter and is latched on MCLK rising edge, synchronization instant (t0) on next MCLK rising edge. 27. TDATA can be delayed from 0 to 63 full bit periods by the CS5376A test bit stream generator. The timing diagram shows no TBSDATA delay.
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DIGITAL CHARACTERISTICS (CONT.)
SYNC
MCLK
(2.048 MHz)
MSYNC
t0
TDATA
(256 kHz)
Figure 2. System Timing Diagram
MCLK
(2.048 MHz) tmss tmsh tmclk
MSYNC
t0
tmsync
TDATA
(256 kHz) ttdata
Figure 3. MCLK / MSYNC Timing Detail
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POWER SUPPLY CHARACTERISTICS
Parameter AC Mode Supply Current (MODE = 1, 2, 3, 6) Analog Power Supply Current Digital Power Supply Current DC Mode Supply Current (MODE = 4) Analog Power Supply Current Digital Power Supply Current DC Mode Supply Current (MODE = 5) Analog Power Supply Current Digital Power Supply Current Sleep Mode Supply Current (MODE = 0, 7) Analog Power Supply Current Digital Power Supply Current Power Down Supply Current (MCLK = 0) Analog Power Supply Current Digital Power Supply Current Time to Enter Power Down (MCLK disabled) Power Supply Rejection Power Supply Rejection Ratio (Note 29) PSRR 90 dB (Note 28) (Note 28) (Note 8) IA ID PDTC 1 20 40 A A S (Note 28) (Note 28) IA ID 200 260 A A (Note 28) (Note 28) IA ID 4.2 20 mA A (Note 28) (Note 28) IA ID 2.7 20 mA A (Note 28) (Note 28) IA ID 8 20 10 mA A Symbol Min Typ Max Unit
Notes: 28. All outputs unloaded. Digital inputs forced to VD or DGND respectively. 29. Power supply rejection is characterized by applying a 100 mVp-p 50-Hz sine wave to each supply.
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VA+ MODE(0, 1, 2) ATT(0, 1, 2) VD
TDATA Attenuator
OUT+ OUT24-Bit DAC BUF+ BUF-
VREF+ VREFClock Generator MCLK MSYNC
VA-
CAP+ CAP-
GND
Figure 4. CS4373A Block Diagram
2. GENERAL DESCRIPTION
The CS4373A is a differential output digital-toanalog converter with multiple operational modes and programmable output attenuation. It provides self-test and precision calibration capability for high-resolution, low-frequency measurement systems designed from CS3301A / CS3302A differential amplifiers, CS5371A / CS5372A modulators, and the CS5376A digital filter. 2.1 Digital Inputs The CS4373A is driven by a digital bit stream from the CS5376A digital filter test bit stream (TBS) generator. The digital filter also provides clock and sync signals as well as GPIO control signals to set the operational mode and attenuation. 2.2 Analog Outputs Two sets of differential analog outputs, OUT and BUF, simplify system design as dedicated outputs for testing the electronics channel and for in-circuit sensor tests. Output attenuator settings are binary weighted (1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64) and match the CS3301A / CS3302A amplifier input levels for full-scale testing at all gain ranges. For maximum performance, the precision outputs (OUT) must drive only high-impedance loads such as the CS3301A / CS3302A amplifier inputs. The buffered outputs (BUF) can drive lower-impedance loads, down to 1 k, but with reduced performance compared to the precision outputs. 2.3 Multiple Operational Modes The CS4373A operates in either AC or DC test modes. AC test modes (MODE 1, 2, 3, 6) are used to measure system THD and CMRR performance. DC test modes (MODE 4, 5) are for gain calibration and pulse tests. 2.4 Low Power The CS4373A is optimized for low-power operation and has a restricted operational bandwidth in the AC modes. For stable operation, full-scale AC test signals must not contain frequencies above 100 Hz. AC test signals above 100 Hz (TBS impulse mode, for example) must have a -20 dB reduced amplitude to ensure stability of the CS4373A low-power architecture.
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3. SYSTEM DIAGRAMS
Geophone or Hydrophone Sensor
M U X
CS3301A CS3302A AMP CS5371A CS5372A System Telem etry Modulator
Geophone or Hydrophone Sensor
M U X
CS3301A CS3302A AMP
CS5376A
Controller or Configuration EEPROM
Digital Filter Geophone or Hydrophone Sensor M U X CS3301A CS3302A AMP CS5371A CS5372A Modulator Com m unication Interface
Geophone or Hydrophone Sensor
M U X
CS3301A CS3302A AMP
CS4373A
Switch Switch MUX MUX
Test DAC
Figure 5. System Diagram
VA+ SWITCH CONTROL SENSOR CH1 BUF CH2 BUF CH3 BUF CH4 BUF ELECTRONICS CH1,2,3,4 OUT VA+ 10 10nF C0G
0.1F VACAP+ CAPVD
0.1F
VD
MCLK MSYNC TDATA
MCLK MSYNC TBSDATA
Analog Switches
Route BUF as diff pair
BUF+ BUF-
CS4373A
Route OUT as diff pair OUT+ OUTRoute VREF as diff pair 100F + VAVAVREF+ VREFMODE0 MODE1 MODE2 ATT0 ATT1 ATT2 DGND
GPIO GPIO GPIO GPIO GPIO GPIO
2.5 V VREF
VA-
0.1F
CS5376A SIGNALS
Figure 6. Connection Diagram
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POWER DOWN MCLK = OFF MODE = XXX
SLEEP MODES MCLK = ON MODE = 0, 7
AC TEST MODES MCLK = ON MODE = 1, 2, 3, 6
DC TEST MODES MCLK = ON MODE = 4, 5
Figure 7. Power Mode Diagram
4. POWER MODES
The CS4373A has four power modes. AC test modes and DC test modes are operational modes, while the power down and sleep modes are non-operational, standby modes. 4.1 Power Down If MCLK is stopped, an internal loss-of-clock detection circuit automatically places the CS4373A into power down. Power down is independent of the MODE and ATT pin settings, and is automatically invoked after approximately 40 s without an incoming MCLK edge. In power down the AC and DC test circuitry is inactive and the analog outputs are high impedance. When used with the CS5376A digital filter, the CS4373A is powered down immediately after reset since MCLK is disabled by default. 4.2 Sleep Modes With MCLK enabled, selecting either of the sleep modes (MODE 0, 7) places the CS4373A into a micropower sleep state. Following completion of the AC and DC system self-tests, the CS4373A is typically set into sleep mode for normal data acquisition. In sleep mode the AC and DC test circuitry is inactive and the analog outputs are high impedance. 4.3 AC Test Modes With MCLK and TDATA active, selecting an AC test mode (MODE 1, 2, 3, 6) causes the CS4373A to output AC waveforms on the enabled analog outputs. AC test modes use the low-power circuitry in the CS4373A to create precision differential or common mode analog AC output signals from the encoded digital test bit stream (TBS) input. 4.4 DC Test Modes With MCLK active, selecting a DC test mode (MODE 4, 5) causes the CS4373A to generate precision DC voltages on the analog outputs. DC test modes use switch-capacitor levelshifting buffer circuitry in the CS4373A to create differential or common mode DC analog output voltages from the voltage reference input.
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5. OPERATIONAL MODES
The CS4373A has six operational modes and two sleep modes selected by the MODE2, MODE1, and MODE0 pins. only the BUF analog output is enabled, and OUT is high impedance.
OUT+ OUT-
Selection MODE[2:0] 0 1 2 3 4 5 6 7 000 001 010 0 11 100 101 11 0 111
Mode Description Sleep mode. AC OUT and BUF outputs. AC OUT only, BUF high-z. AC BUF only, OUT high-z. DC common mode output. DC differential output. AC common mode output. Sleep mode.
Maximum 5 Vpp Differential
CS4373A MODE 1
BUF+ BUFMaximum 5 Vpp Differential
OUT+ OUT-
Maximum 5 Vpp Differential
Table 2. Operational Modes
CS4373A MODE 2
BUF+ BUFHigh Impedance
5.1 Sleep Modes Sleep modes (MODE 0, 7) save power during normal acquisition by turning off the AC and DC test circuitry after system self-tests are complete. In sleep mode the OUT and BUF analog outputs are high impedance. 5.2 AC Test Modes AC test modes use the digital test bit stream (TBS) input from the CS5376A digital filter to construct analog AC waveforms. The digital bit stream input to the TDATA pin encodes the analog waveform as over-sampled one bit data, which is then converted into precision differential or common mode analog AC signals by the CS4373A. 5.2.1 AC Differential The first three AC test modes (MODE 1, 2, 3) create precision differential analog signals for THD and impulse testing of the measurement channel. In mode 1, both sets of differential analog outputs (OUT and BUF) are enabled. In mode 2 only the OUT analog output is enabled, and BUF is high impedance. In mode 3
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OUT+ OUT-
High Impedance
CS4373A MODE 3
BUF+ BUFMaximum 5 Vpp Differential
Figure 8. AC Differential Modes
Differential AC signals out of the CS4373A consist of two halves with equal but opposite magnitude, varying about a common mode voltage. A full-scale 5 VPP differential AC signal centered on a -0.15 V common mode voltage will have: SIG+ = -0.15 V + 1.25 V = +1.1 V SIG- = -0.15 V - 1.25 V = -1.4 V SIG+ is +2.5 V relative to SIG19
CS4373A
For the opposite case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = +1.1 V SIG+ is -2.5 V relative to SIGSo the total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar calculation can be done for SIG- relative to SIG+. It's important to note that a 5 Vpp differential signal centered on a -0.15 V common mode voltage never exceeds +1.1 V with respect to ground and never drops below -1.4 V with respect to ground on either half. By definition, differential voltages are measured with respect to the opposite half, not relative to ground. A voltmeter differentially measuring between SIG+ and SIG- in the above example would read 1.767 Vrms, or 5 Vpp. 5.2.2 AC Common Mode The final AC test mode (MODE 6) creates a matched AC common mode analog signal for CMRR testing of the measurement channel. In mode 6, both sets of analog outputs (OUT and BUF) are enabled. There is no common mode AC waveform output for an attenuator setting of 1/64. verted to a measurable differential signal at the fundamental frequency. 5.2.3 AC Stability For the CS4373A low-power architecture to remain stable, the TDATA input bit stream should only encode 100 Hz or lower bandwidth analog signals. For TDATA bit stream frequencies above 100 Hz (for example, TBS impulse mode), the encoded amplitude must be reduced -20 dB below full scale to guarantee stability. If the CS4373A low-power architecture becomes unstable, persistent elevated noise will be present on the analog outputs and AC linearity will be poor. To recover stability, place the CS4373A into power down or sleep mode and restart the CS5376A test bit stream generator before placing the CS4373A back into an AC test mode. 5.3 DC Test Modes DC test modes create precision level-shifted and buffered versions of the voltage reference input as precision DC common mode and DC differential analog outputs. The absolute accuracy of the DC test modes is highly dependent on the absolute accuracy of the voltage reference input voltage. 5.3.1 DC Common Mode The first DC test mode (MODE 4) creates a matched DC common mode analog output voltage as a baseline measurement for gain calibration and differential pulse tests. In mode 4, both sets of analog outputs (OUT and BUF) are enabled. 5.3.2 DC Differential The second DC test mode (MODE 5) creates a precision differential DC analog output voltage as the final measurement for gain calibration and as the step/pulse output for differential pulse tests. In mode 5, both sets of analog outputs (OUT and BUF) are enabled.
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OUT+ OUT-
Maximum 2.5 Vpp Common Mode
CS4373A MODE 6
BUF+ BUFMaximum 2.5 Vpp Common Mode
Figure 9. AC Common Mode
Gross leakage in the sensor channel can be detected by applying a full-scale AC common mode signal. If there is a significant differential mismatch in the channel due to sensor leakage, the AC common mode signal will be con20
CS4373A
In DC differential output mode (MODE 5) the level-shifting buffer circuitry adds low-level 32 kHz switched-capacitor noise to the DC output. This noise is out of the measurement bandwidth for systems designed with CS3301A / CS3302A amplifiers and CS5371A / CS5372A modulators, and is rejected by the CS5376A digital filter. This 32 kHz switch-capacitor noise does not affect DC system tests, though it may be visible on an oscilloscope at high gain levels. channel. By first measuring the differential offset of the DC common mode output (MODE 4) and then measuring the DC differential mode amplitude (MODE 5), a precise offset corrected volts-to-codes conversion ratio can be calculated. This known ratio is then used to normalize the full-scale amplitude using the CS5376A digital filter GAIN registers to match other channels in the measurement network. By switching between DC common mode (MODE 4) and DC differential mode (MODE 5), pulse waveforms can be created to characterize the step response of the measurement channel. If a pulse test requires precise timing control, an external controller should directly toggle the MODE pins of the CS4373A to avoid delays associated with writing to the CS5376A digital filter GPIO registers. Sensor impedance can be measured using DC differential mode (MODE 5), provided matched series resistors are installed between the BUF analog outputs and the sensor. Applying the known DC differential voltage to the resistor-sensor-resistor string permits a ratiometric sensor impedance calculation from the measured voltage drop across the sensor. Switching between DC differential mode (MODE 5) and sleep mode (MODE 0, 7) can, in the case of a moving-coil geophone, test basic parameters of the electro-mechanical transfer function. The voltage relaxation characteristic of the sensor when switching the analog outputs from a differential DC voltage to high impedance depends primarily on the geophone resonant frequency and damping factor.
OUT+ OUT-
Approx -0.15 VDC Common Mode
CS4373A MODE 4
BUF+ BUFApprox -0.15 VDC Common Mode
OUT+ OUT-
Maximum 2.5 VDC Differential
CS4373A MODE 5
BUF+ BUFMaximum 2.5 VDC Differential
Figure 10. DC Test Modes
By measuring both DC test modes (MODE 4, 5), precision gain-calibration coefficients can be calculated for the measurement
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CS4373A
VA+ SWITCH CONTROL SENSOR CH1 BUF CH2 BUF CH3 BUF CH4 BUF ELECTRONICS CH1,2,3,4 OUT VA+ 10 Route OUT as diff pair OUT+ OUTRoute VREF as diff pair 100F + VAVAVA0.1F VREF+ VREF10nF C0G VD
0.1F VACAP+ CAPVD
0.1F
MCLK MSYNC TDATA
MCLK MSYNC TBSDATA
Analog Switches
Route BUF as diff pair
BUF+ BUF-
CS4373A
MODE0 MODE1 MODE2 ATT0 ATT1 ATT2 DGND
GPIO GPIO GPIO GPIO GPIO GPIO
2.5 V VREF
CS5376A SIGNALS
Figure 11. Digital Inputs
6. DIGITAL INPUTS
The CS4373A is designed to operate with the CS5376A digital filter. The digital filter generates one-bit test bit stream data (TDATA), a master clock (MCLK) and a synchronization signal (MSYNC). In addition, the digital filter GPIO pins control the CS4373A operational mode (MODE) and attenuator (ATT) settings. 6.1 TDATA Connection The TDATA digital input expects encoded one-bit data nominally at a 256 kHz rate. The one's density input range is approximately 25% minimum to 75% maximum, with differential mid-scale at 50% one's density. The CS5376A digital filter test bit stream (TBS) generator can encode two types of AC signals as over-sampled, one-bit data - a pure sine wave for THD and CMRR testing or a triggerable impulse waveform for synchronization testing and impulse response characterization. In the AC operational modes, the CS4373A converts the over-sampled bit stream digital data into precision differential or common mode analog AC signals. The CS5376A TBS sine mode encodes an approximately 5 Vpp full-scale sine wave signal with a digital filter TBSGAIN register setting of 0x04B8F2. Because TBS impulse mode encodes frequencies above 100 Hz, a maximum 0x0078E5 TBSGAIN impulse mode register setting is specified to guarantee stability of the
22
CS4373A low-power circuitry. Details on the setup and operation of the digital filter TBS generator can be found in the CS5376A data sheet. 6.2 MCLK Connection The CS5376A digital filter generates the master clock for CS4373A, typically 2.048 MHz, from a synchronous CLK input from the external system. By default, MCLK is disabled at reset and is enabled by writing the digital filter CONFIG register. If MCLK is disabled during operation, the CS4373A will enter power down after approximately 40 S. MCLK must have low in-band jitter to guarantee full analog performance, requiring a crystal- or VCXO-based system clock into the digital filter. Clock jitter on the digital filter external CLK input directly translates to jitter on MCLK. 6.3 MSYNC Connection The CS5376A digital filter also provides a synchronization signal to the CS4373A. The MSYNC signal is generated following a rising edge received on the digital filter SYNC input. By default MSYNC generation is disabled at reset and is enabled by writing to the digital filter CONFIG register. The input SYNC signal to the CS5376A digital filter sets a common reference time t0 for meaDS699F2
CS4373A
surement events, thereby synchronizing analog sampling across a measurement network. The timing accuracy of the input SYNC signal from measurement node to measurement node must be +/- 1 MCLK to maximize MSYNC analog sample synchronization accuracy. The CS4373A MSYNC input is rising-edge triggered and resets the internal MCLK counter/divider to guarantee synchronous operation with other system devices. While the MSYNC signal synchronizes the internal operation of the CS4373A, by default, it does not synchronize the phase of the encoded digital test bit stream (TBS) sine wave unless enabled in the digital filter TBSCFG register. 6.4 GPIO Connections The CS5376A controls 12 general-purpose input output (GPIO) pins through the digital filter GPCFG registers. These GPIO pins are typically assigned to operate the CS4373A mode and attenuator pins, along with the CS3301A / CS3302A amplifiers input mux and gain pins. The gain and attenuation settings of the CS3301A / CS3302A amplifiers and CS4373A are identically decoded to allow fullscale performance testing at all system gain ranges with shared GAIN and ATT control signals. If precise timing control of operational modes is required (for example, switching between DC modes for pulse generation), an external controller should directly toggle the MODE pins of the CS4373A to avoid the delay associated with writing to the CS5376A digital filter GPCFG registers.
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CS4373A
VA+ SWITCH CONTROL SENSOR CH1 BUF CH2 BUF CH3 BUF CH4 BUF ELECTRONICS CH1,2,3,4 OUT VA+ 10 10nF C0G VD
0.1F VACAP+ CAPVD
0.1F
MCLK MSYNC TDATA
MCLK MSYNC TBSDATA
Analog Switches
Route BUF as diff pair
BUF+ BUF-
CS4373A
Route OUT as diff pair OUT+ OUTRoute VREF as diff pair 100F + VAVAVREF+ VREFMODE0 MODE1 MODE2 ATT0 ATT1 ATT2 DGND
GPIO GPIO GPIO GPIO GPIO GPIO
2.5 V VREF
VA-
0.1F
CS5376A SIGNALS
Figure 12. Analog Outputs
7. ANALOG OUTPUTS
The CS4373A has multiple differential analog outputs. The best possible analog performance is achieved from the precision outputs (OUT), but with only minimal drive capability. A buffered output (BUF) can drive an external load, but with reduced analog performance. The internal anti-alias filter requires a dedicated capacitor connection (CAP) to eliminate undesired high-frequency signals. 7.1 Differential Signals Differential AC signals out of the CS4373A consist of two halves with equal but opposite magnitude varying about a common mode voltage. A full-scale 5 VPP differential AC signal centered on a -0.15 V common mode voltage will have: SIG+ = -0.15 V + 1.25 V = +1.1 V SIG- = -0.15 V - 1.25 V = -1.4 V SIG+ is +2.5 V relative to SIGFor the opposite case: SIG+ = -0.15 V - 1.25 V = -1.4 V SIG- = -0.15 V + 1.25 V = +1.1 V SIG+ is -2.5 V relative to SIGSo the total swing for SIG+ relative to SIG- is (+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar calculation can be done for SIG- relative to SIG+. It's important to note that a 5 Vpp differential signal centered on a -0.15 V common
24
mode voltage never exceeds +1.1 V with respect to ground and never drops below -1.4 V with respect to ground on either half. By definition, differential voltages are measured with respect to the opposite half, not relative to ground. A voltmeter differentially measuring between SIG+ and SIG- in the above example would read 1.767 Vrms, or 5 Vpp. 7.2 Analog Output Attenuation The CS4373A has seven analog output attenuation settings from 1/1 to 1/64 selected with the ATT2, ATT1, and ATT0 pins. At 1/64 attenuation in AC Common Mode (MODE 6) there is no output signal amplitude due to the attenuator architecture.
Selection ATT[2:0] 0 1 2 3 4 5 6 7 000 001 010 0 11 100 101 11 0 111 Attenuation 1/1 1/2 1/4 1/8 1/16 1/32 1/64 reserved dB 0 dB -6.02 dB -12.04 dB -18.06 dB -24.08 dB -30.10 dB -36.12 dB reserved
Table 3. Output Attenuation Settings
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When enabled, attenuation is applied to both the OUT and BUF differential analog outputs. The OUT pins connect directly into the internal attenuator resistors and so attenuation accuracy is highly sensitive to load impedance on the OUT pins. Loading on the BUF pins does not affect attenuator accuracy. The attenuation settings of CS4373A match the gain ranges of the CS3301A / CS3302A differential amplifiers to enable full-scale testing at all gain ranges. The CS3301A / CS3302A amplifier gain settings (GAIN) are decoded identical to the CS4373A attenuator settings (ATT) and so can share GPIO signals from the digital filter. 7.3 OUT Precision Output The OUT pins are precision differential analog outputs for testing the high-performance electronics measurement channel. These precision outputs have higher performance specifications than the BUF outputs, but with a much higher sensitivity to external loading. Excessive resistive or capacitive loading on the OUT pins will degrade the analog performance characteristics of the CS4373A in all operational modes. The OUT precision output is optimized for direct connection to the CS3301A / CS3302A amplifier differential inputs, which have very high input impedance. These amplifiers include a pin-controlled input multiplexer to switch between an internal differential termination for noise tests and two external differential inputs. One external amplifier input is typically dedicated to sensor measurements and the other to testing the electronics channel. The OUT outputs are enabled in all operational modes except "AC BUF Only" mode (MODE 3) and sleep modes (MODE 0, 7). In AC BUF Only and sleep modes the OUT pins are high impedance. 7.4 BUF Buffered Output The BUF pins are buffered differential analog outputs for testing external sensors such as geophones or hydrophones. The buffered outputs have reduced performance specifications compared with the OUT outputs, but are less sensitive to external loading. The BUF outputs are enabled in all operational modes except "AC OUT Only" mode (MODE 2) and sleep modes (MODE 0, 7). In AC OUT Only and sleep modes the BUF pins are high impedance to ensure they do not interfere with sensor operation during normal data acquisition. For sensor impedance testing, it is required to place matched series resistors in between the BUF outputs and the differential sensor. With known series resistors and a known DC differential source voltage, sensor resistance can be calculated ratiometrically from the measured voltage drop across the sensor. 7.5 CAP Analog Output The CS4373A requires a 10 nF C0G or NPOtype capacitor connected differentially across the CAP pins. This capacitor creates an internal anti-alias filter to eliminate high-frequency signals from the OUT and BUF analog outputs and helps to maintain the stability of the low-power circuitry. A COG, NPO or similar high-quality capacitor is required for CAP since other capacitor types, such as X7R, do not have the required linearity. Using a poor-quality capacitor on CAP will significantly degrade THD performance in the AC operational modes.
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25
CS4373A
To VA+ Regulator
100 F
0.1 F 10 2.500 V VREF 0.1 F
Route VREF as a differential pair from the 100uF RC filter capacitor
+ 100 F
0.1 F
To VREF+
To VARegulator
100 F
0.1 F
0.1 F
To VREF-
Figure 13. Voltage Reference Circuit
8. VOLTAGE REFERENCE
The CS4373A requires a 2.500 V precision voltage reference to be supplied to the VREF pins. 8.1 VREF Power Supply To guarantee proper regulation headroom for the voltage reference device, the voltage reference GND pin should be connected to VA- instead of system ground, as shown in Figure 13. This connection results in VREFvoltage equal to VA- and VREF+ voltage very near ground potential [(VA-) + 2.500 VREF]. Power supply inputs to the voltage reference device should be bypassed to system ground with 0.1 F capacitors placed as close as possible to the power and ground pins. In addition to 0.1 F local bypass capacitors, at least 100 F of bulk capacitance to system ground should be placed on each power supply near the voltage regulator outputs. Bypass capacitors should be X7R, C0G, tantalum, or other high-quality dielectric type. 8.2 VREF RC Filter A primary concern in selecting a precision voltage reference is noise performance in the measurement bandwidth. The Linear Technology LT1019AIS8-2.5 voltage reference yields acceptable noise levels if the output is filtered with a low-pass RC filter. A separate RC filter is required for each system device connected to a given voltage reference. By sharing a common RC filter, signaldependent sampling of the voltage reference by one system device could cause unwanted tones to appear in the measurement bandwidth of another system device via common impedance coupling. 8.3 VREF PCB Routing To minimize the possibility of outside noise coupling into the CS4373A voltage reference input, the VREF traces should be routed as a differential pair from the large capacitor of the voltage reference RC filter. Careful control of the voltage reference source and return currents by routing VREF as a differential pair will improve immunity from external noise. To further improve noise rejection of the VREF routing, include 0.1 F bypass capacitors to system ground as close as possible to the VREF+ and VREF- pins of the CS4373A.
26
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8.4 VREF Input Impedance The switched-capacitor input architecture of the VREF inputs results in an input impedance that depends on the internal capacitor size and the clock frequency. With a 15 pF internal capacitor and a 2.048 MHz MCLK the VREF input impedance is approximately [1 / [(2.048 MHz) * (15 pF)]] = 32 k. While the size of the internal capacitor is fixed, the voltage reference input impedance will vary with MCLK. The voltage reference external RC filter series resistor creates a voltage divider with the VREF input impedance to reduce the effective applied input voltage. To minimize gain error resulting from this voltage divider effect, the RC filter series resistor should be the minimum size recommended in the voltage reference device data sheet. 8.5 VREF Accuracy The nominal voltage reference input is specified as 2.500 V across the VREF pins, and all CS4373A gain accuracy specifications are measured with a nominal voltage reference input. Any variation from a nominal VREF input will proportionally vary the analog full-scale gain accuracy. Since temperature drift of the voltage reference results in gain drift of the analog full-scale amplitude, care should be taken to minimize temperature drift effects through careful selection of passive components and the voltage reference device itself. Gain drift specifications of the CS4373A do not include the temperature drift effects of external passive components or of the voltage reference device itself. 8.6 VREF Independence If the test signal source is required to be fully independent of the measurement channel, a separate voltage reference device for the CS4373A is required. Using a separate voltage reference minimizes the possibility of undetected ratiometric errors when the same voltage reference is used by both the test signal source and the measurement channel. Because modern precision voltage references are highly reliable, requirements for separate modulator and test DAC voltage references should be considered carefully. In the unlikely event of voltage reference failure independent of other system components, the CS4373A volts-to-codes ratio will be out of spec and performance will be poor during system self-tests.
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27
CS4373A
To VA+ Regulator 100 uF 0.1 uF VA+ VD 0.1 uF 100 uF To VD Regulator
CS4373A
VATo VARegulator 100 uF 0.1 uF GND
Figure 14. Power Supply Diagram
9. POWER SUPPLIES
The CS4373A has a positive analog power supply pin (VA+), a negative analog power supply pin (VA-), a digital power supply pin (VD), and a ground pin (GND). For proper operation, power must be supplied to all power supply pins, and the ground pin must be connected to system ground. The CS4373A digital power supply (VD) and the CS5376A digital power supplies (VDD1 / VDD2) must share a common power supply voltage. 9.1 Power Supply Bypassing The VA+, VA-, and VD power supplies should be bypassed to system ground with 0.1 F capacitors placed as close as possible to the power pins of the device. In addition to the 0.1 F local bypass capacitors, at least 100 F bulk capacitance to system ground should be placed on each power supply near the voltage regulator output, with additional power supply bulk capacitance placed among the analog component route if space permits. Bypass capacitors should be X7R, C0G, tantalum, or other high-quality dielectric type. 9.2 PCB Layers and Routing The CS4373A is a high-performance device, and special care must be taken to ensure power and ground routing is correct. Power can be supplied either through dedicated power
28
planes or routed traces. When routing power traces, it is recommended to use a "star" routing scheme with the star point either at the voltage regulator output or at a local power supply bulk capacitor. It is also recommended to dedicate a full PCB layer to a solid ground plane, without splits or routing. All bypass capacitors should connect between the power supply circuit and the solid ground plane as near as possible to the device power supply pins. The CS4373A analog outputs are differentially routed and do not normally require connection to a separate analog ground. However, if a separate analog ground is required, it should be routed using a "star" routing scheme on a separate layer from the solid ground plane and connected to the ground plane only at the star point. Be sure all active devices and passive components connected to the analog ground are included in the "star" route to ensure sensitive analog currents do not return through the ground plane. 9.3 Power Supply Rejection Power supply rejection of the CS4373A is frequency dependent. The CS5376A digital filter rejects power supply noise for frequencies above the selected digital filter corner frequency. Power supply noise frequencies between DC and the digital filter corner frequency are
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CS4373A
rejected as specified in Power Supply Characteristics table. the are battery powered and utilize DC-DC converters to efficiently generate power supply voltages. To minimize interference effects, operate the DC-DC converter at a frequency which is rejected by the digital filter, or operate it synchronous to the MCLK rate. A synchronous DC-DC converter whose operating frequency is derived from MCLK will theoretically minimize the potential for "beat frequencies" to appear in the measurement bandwidth. However this requires the source clock to remain jitter-free within the DC-DC converter circuitry. If clock jitter can occur within the DC-DC converter (as in a PLL-based architecture), it's better to use a nonsynchronous DC-DC converter whose switching frequency is rejected by the digital filter. During PCB layout, do not place high-current DC-DC converters near sensitive analog components. Carefully routing a separate DC-DC "star" ground will help isolate noisy switching currents away from the sensitive analog components.
9.4 SCR Latch-up The VA- pin is tied to the CS4373A CMOS substrate and must always be the most-negative voltage applied to the device to ensure SCR latch-up does not occur. In general, latch-up may occur when any pin voltage exceeds the limits of the Absolute Maximum Ratings table. It is recommended to connect the VA- power supply to system ground (GND) with a reverse-biased Schottky diode. At power up, if the VA+ power supply ramps before the VAsupply is established, the VA- pin voltage could be pulled above ground potential through the CS4373A device. If the VA- supply is pulled 0.7 V or more above GND, SCR latch-up can occur. A reverse-biased Schottky diode will clamp the VA- voltage a maximum of 0.3 V above ground to ensure SCR latch-up does not occur at power up. 9.5 DC-DC Converters Many low-frequency measurement systems
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CS4373A
10. TERMINOLOGY
* Signal-to-Noise Ratio (Dynamic Range) - Ratio of the rms magnitude of the full-scale signal to the integrated rms noise from DC to 430 Hz. The following formula is used to calculate SNR:
SNR = 20log
*
Total Harmonic Distortion - Ratio of the power of the fundamental frequency to the sum of the powers of all harmonic frequencies from DC to 430 Hz. The following formula is used to calculate THD:
THD = 10log
*
Full-scale Bandwidth - The bandwidth in which the converter can generate a full-scale signal while maintaining performance specifications.
*
Impulse Amplitude - The maximum amplitude of the output signal beyond the full-scale bandwidth.
*
Differential Output Level - The voltage between the analog output pins of the device.
*
Full-scale Accuracy - Variation in the measured output voltage from the theoretical full-scale output voltage at 1x attenuation. The following formula is used to calculate full-scale accuracy:
full scale accuracy =
*
*100%
Relative Accuracy - Variation in the measured output voltage from the theoretical attenuated output voltage at each of the attenuation ranges. The following formula is used to calculate relative accuracy:
measured attenuated voltage - theoretical attenuated voltage relative accuracy = theoretical attenuated voltage (relative to the measured full scale voltage) *100%
*
Full Scale Drift - The variation of the measured full-scale voltage across the specified temperature range.
*
Common Mode Drift - The variation in the measured common mode voltage across the specified temperature range.
30
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|
(
(
|
(
( measured full scale voltage - theoretical full scale voltage theoretical full scale voltage
(
of the harmonic frequencies ( sum of the powers fundamental frequency power of the
(
full scale signal ( rms magnitude of of noise floor rms magnitude
|
|
CS4373A
11. PIN DESCRIPTION
Positive Capacitor Output Negative Capacitor Output Positive Buffered Output Negative Buffered Output Positive High Precision Output Negative High Precision Output Positive Analog Power Supply Negative Analog Power Supply Negative Voltage Reference Positive Voltage Reference No Connect No Connect No Connect No Connect CAP+ CAPBUF+ BUFOUT+ OUTVA+ VAVREFVREF+ NC NC NC NC GND MODE0 MODE1 MODE2 ATT0 ATT1 ATT2 TDATA VD GND MCLK MSYNC DNC DNC System Ground Mode Select Mode Select Mode Select Attenuation Range Select Attenuation Range Select Attenuation Range Select Signal Bitstream Input Positive Digital Power Supply System Ground Master Clock Input Master Sync Input Do Not Connect Do Not Connect
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Pin Name
Pin # I/O 1 2 3 4 5 6 7 8 9 10 17 18 19 20 21 I
Pin Description
CAP+, CAPBUF+, BUFOUT+, OUTVA+, VAVREF-, VREF+ MSYNC MCLK GND VD TDATA
O Capacitor connection for internal anti-alias filter. O Buffered differential analog output. O Precision differential analog output. I
Analog power supply. Refer to the Specified Operating Conditions. Voltage reference input. Refer to the Specified Operating Conditions. Master Sync Input. Low to high transition resets the internal clock phasing. Master Clock Input. CMOS compatible clock input. System ground. Digital power supply. Refer to the Specified Operating Conditions. Test Bit Stream input from digital filter TBS generator.
I
I
I
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CS4373A
Pin Name Pin # I/O 22, 23, 24 I Pin Description Attenuation Range. Selects the output attenuation range. Attenuation Selection 0 1 2 3 4 5 6 7 ATT[2:0] 000 001 010 0 11 100 101 11 0 111 Attenuation 1/1 1/2 1/4 1/8 1/16 1/32 1/64 reserved dB 0 dB -6.02 dB -12.04 dB -18.06 dB -24.08 dB -30.10 dB -36.12 dB reserved
ATT2, ATT1, ATT0
MODE2, MODE1, MODE0
25, 26, 27
I
Mode Selection. Determines the operational mode of the device. Selection 0 1 2 3 4 5 6 7 MODE[2:0] 000 001 010 0 11 100 101 11 0 111 Mode Description Sleep mode. AC OUT and BUF outputs. AC OUT only, BUF tri-state. AC BUF only, OUT tri-state. DC common mode output. DC differential output. AC common mode output. Sleep mode.
GND
28
System ground.
32
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CS4373A
12. PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b
2
END VIEW
SIDE VIEW
123
SEATING PLANE
TOP VIEW
DIM A A1 A2 b D E E1 e L
MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0
INCHES NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4
MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8
MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.15 1.75 -10.20 7.80 5.30 0.65 0.90 4
NOTE MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8
2,3 1 1
JEDEC #: MO-150 Controlling Dimension is Millimeters Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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CS4373A
13.ORDERING INFORMATION
Model Temperature Package
CS4373A-ISZ (lead free)
-40 to +85 C
28-pin SSOP
14.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp MSL Rating* Max Floor Life
CS4373A-ISZ (lead free)
260 C
3
7 Days
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
15.REVISION HISTORY
Revision PP1 PP2 PP3 F1 F2 Date MAR 2003 SEP 2005 NOV 2005 DEC 2005 DEC 2006 Preliminary release for CS4373. Update for new CS4373A features and most-current characterization data. Remove references to CS5378. Update for most-current characterization data. Updated with final characterization data. Updated to final status with most-recent characterization data for Cirrus QPL process. Changes
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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